The drive for miniaturization of integrated circuit (IC) assemblies such as dies has created a similar drive to provide dense interconnections between dies in a package assembly. For example, interposers and bridges such as Embedded Multi-die Interconnect Bridge (EMIB) technologies are emerging to provide dense interconnect routing between dies or other electrical components. Such interposers and bridges may take advantage of semiconductor processing (e.g., CMOS) techniques to form dense interconnect routing features. However, such interconnection routing features may be highly lossy and capacitive, which may cause a signal rise time to decrease quadratically with a routing length and degrade power efficiency. For example, in some cases, every 0.16 picoFarad (pF) of capacitance may degrade power efficiency by as much as 0.1 picojoules per bit (pJ/b). While thicker dielectric materials and lower dielectric constants may help mitigate this effect, such changes to present processing scenarios may be risky and/or costly. Other techniques to reduce capacitance and time constant of interconnects to achieve higher signaling rates and power efficiency are needed. Routing configurations in interposers and bridges may be based on a layout design rule for Design For Manufacturing (DFM), which may facilitate fabrication with improved yields.